Modeling, Fabrication, and Characterization of Memristors
Digital Document
Document
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Handle
http://hdl.handle.net/11134/20002:860648932
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Persons |
Persons
Creator (cre): Mazady, Anas
Major Advisor (mja): Anwar, Mehdi
Associate Advisor (asa): Taylor, Geoff
Associate Advisor (asa): Chandy, John
Associate Advisor (asa): Forte, Demenic
Associate Advisor (asa): Tehranipoor, Mark
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Title |
Title
Title
Modeling, Fabrication, and Characterization of Memristors
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Origin Information
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Parent Item
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Resource Type
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Digital Origin |
Digital Origin
born digital
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Description |
Description
The term �memristor� was coined by L. Chua from its two distinct functional characteristics, memory and resistor. From the symmetry argument of the circuit element and circuit variable matrix, memristor is deemed as the fourth fundamental circuit element, after resistor, capacitor, and inductor. Memristor switching and observed I-V characteristics are explained utilizing the underlying physics of the device in terms of the formation and rupture of filaments. Three different conduction mechanisms, namely - filament assisted tunneling current, bulk tunneling current and currents flowing through low and high conductivity filaments give rise to the total current in memristive systems. DC and RF performance of memristor circuits, including transient behavior, is developed by taking into account these current contributions arising from different conduction mechanisms. The DC circuit model explains the observed I-V hysteresis and most importantly allows scaling and optimization. RF analysis suggests for a maximum allowable frequency of 7.5 GHz beyond which TiO2 memristors can no longer be used as RRAMs. Transient performance of memristors employing different material systems is investigated and experimentally verified using ZnO nanowire memristors. ZrOx memristors showed the shortest switching delay owing to its high mobility of 370 cm2/V-s. Upon scaling devices down to 50 nm, the delay decreases by 3-4 orders of magnitude. Bipolar resistive switching with ROFF/RON ratio of 684 and rise and fall times shorter than 7�s and 10�s, respectively, is demonstrated for 2 �m ZnO nanowire memristors. Use of nanowire instead of thin films allows high packing density and as a result high bit density. Experimental demonstration of a 1-bit memristor PUF is reported for the first time implementing ZnO memristors showing 50% uncertainty and high reliability of the response bit for a given challenge. The physics based circuit model of memristors was also implemented to accurately determine the simulation time required for randomly selected polyominoes from a 3D array of memristors. The proposed model provides higher degree of complexity and results in 7 orders of increase in simulation time for an attacker than the previous best report. Operation of a material IMP logic has been demonstrated using only two ZnO memristors that is functional for 5�s logic pulses. Designing logics using memristors allows the use of the same physical unit as multiple functional units, such as � memory, logic, and interconnect. This approach has the potential to redefine the traditional computer architecture to advanced architectures overcoming the �von Neumann bottleneck� of throughput. Chaotic circuit was constructed using only 2 elements, a memristor and a series resistor, which is the most compact form of chaotic circuits ever reported, and demonstrated perfect chaos in its phase-space trajectory with the highest Lyapunov exponent being 61.57s-1.
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Genre
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Organizations
Degree granting institution (dgg): University of Connecticut
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Rights Statement |
Rights Statement
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Use and Reproduction |
Use and Reproduction
These materials are provided for educational and research purposes only.
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Local Identifier |
Local Identifier
OC_d_660
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