Characterization and Mitigation of Resistance Drift in Amorphous Ge2Sb2Te5 Devices at Cryogenic Temperatures

Phase change memory (PCM) is a state-of-the-art high-density, high-speed, high endurance non-volatile memory technology that can potentially bridge the gap between DRAM and flash memory. PCM utilizes the large resistivity contrast between the amorphous and crystalline phases of chalcogenide materials such as Ge2Sb2Te5 (GST) to store information. In order to achieve storage capacity and cost per bit performance similar to existing memory technologies like flash memory, PCM needs stable multi-level per cell (MLC) operation. However, the resistance of the amorphous phase increases with time following a power law. This phenomenon, known as resistance drift, causes multiple resistance levels to overlap with time, resulting in data corruption. In this work, the origin of resistance drift is investigated through characterization of resistance drift in amorphous GST line cells in 125-300 K temperature range. In order to investigate the effect of trapped charges on resistance drift, the amorphized devices are excited with light, which is found to impact resistance drift at 200 K and below. With the application of high electric field, a hysteresis behavior is observed in the current-voltage plots. High field is found to accelerate and stop resistance drift at lower temperatures and significantly reduce resistance drift at room temperature. The presence of resistance drift at cryogenic temperatures, its response to photoexcitation, and acceleration with high electric field suggest that resistance drift is related to charge trapping, at least at cryogenic temperatures. Aside from storage, there has been growing interest in utilizing phase change memory for novel applications. Especially as CMOS scaling is reaching its limits, researchers are investigating new computing architectures to eliminate the bottleneck in the von Neumann architecture. In this work, multi-contact phase change devices that can perform toggle operation are analyzed through 2D electrothermal simulations. These devices can perform toggle flip-flop and multiplexing operations at ~3x lower transistor counts compared to CMOS counterparts and provide the additional benefit of non-volatility. Finally, the functionality of phase change memory line cells as a hardware security primitive: intrinsically reliable physical obfuscated key design, capable of generating reliable random bits is demonstrated by exploiting the limits of the lithography process. To summarize, this thesis provides an understanding of and solution to a major reliability problem and implementation of PCM in applications other than storage.