Quantum Dot Based Multi-Bit FETs and Memories

The demand for compact, high speed, high performance, and low-power requirements pushing the Silicon field-effect transistors (FETs) to its scaling limits. In order to continue Moore’s law in the subnanometer regime, the scaling requires the channel length of FETs to be below 7nm and be able to provide required transistor characteristics and performance, which needs devices beyond Silicon. Devices such as III-V based FETs, Tunnel FETs, 2-D materials based FETs, and Quantum devices are considered as some of the potential replacements for lower technology nodes, but the challenge is that these devices incompatible with existing complementary metal-oxide-semiconductor (CMOS) processing. This dissertation presents an approach to enhance Si devices performance by providing additional functionality in FET transfer characteristics for a particular technology node. This novel functionality is achieved by using cladded quantum dots (QDs) as the FET gate. A quantum dot gate based FET (QDGFET) can process multiple bits or states simultaneously. QDGFET with a combination of ~6nm SiOx-cladded Si and ~4nm GeOx-cladded Ge quantum dots in the gate region has demonstrated four-state behavior, which is two additional output states called intermediate states i1 and i2 between the conventional ON and OFF states. Four-state QDGFETs can be used to realize compact low-power multivalued logic (MVL) circuits with fewer devices. Also, the proposed four-state QDGFET’s fabrication process is compatible with standard CMOS processing technology. Site-specifically self-assemble the quantum dots over the p-Si substrate in the gate region from supernatant colloidal solution. QD size distribution (~6nm for Si) in the supernatant colloidal solution is over 92%. A novel quaternary or two-bit inverter using four-state QDGFET is presented, which demonstrated a 50% saving in the device count and die area. The cladded QDs are also useful to store the charges as a floating gate in nonvolatile memory (NVM) devices. In this dissertation, QD floating gate based nonvolatile memory (QDNVM) structure has been investigated for multi-bit charge storage. A novel quantum dot nonvolatile random access memory (QDNVRAM) structure has also been presented, which demonstrated multi-bit charge storage as well as high-speed and low-voltage erasing. The Erase time reduction has been achieved by incorporating a novel quantum dot channel over the floating gate. A fabricated long channel (10μm X 15μm) QDNVRAM has demonstrated faster Erase times of 4μs-12μs, unlike hundreds of microseconds or few milliseconds in conventional flash memories. The Erase times can be further reduced to nanoseconds by scaling down the QDNVRAM to subnanometers. Fabrication procedures, quantum mechanical simulations and experimental results of four-state QDGFET, 2-bit QDGFET based inverter, multi-bit QDNVM, and QDNVRAM are also presented. Earlier experiments have demonstrated that the QDs can be self-assembled over 35nm X 35nm patterns. Controlled reoxidation and selective etching can be performed to reduce the QDs size to self-assemble over sub-12nm patterns.