Quantum Dot Gate & Quantum Dot Channel FETs: Physics- Based Modeling, Simulation, and Applications

With the ever-increasing demand for processing power in microelectronic-based devices, the economic impact of the microelectronics industry has blossomed over the past decades. However, fabrication of smaller devices has led to new innovation challenges such as the shrinking of critical dimensions, and the effects of defects and impurities have therein. These considerations, as well as methods and materials being employed to address them, have led to immense costs to both the manufacturer and the consumer. It is for these reasons, an alternative approach to Moore’s law is presented; instead of utilizing techniques to decrease the size of the transistor, quantum dot technology, which allows for the creation of devices with intermediate states, is proposed. The use of quantum dots in the gate and/or channel region of an FET demonstrates more processing power, while inhabiting the same spatial constraints of the chip, rather than physically shrinking the device dimensions. The Quantum Dot Gate (QDG) FET comprises of two or more quantum dot layers in the gate region of a conventional nMOS FET, which allows for the formation of intermediate states. The existence of intermediate states affords the devices the ability to be utilized to create more efficient logic circuits. The first part of this thesis will discuss a physics-based model of both a QDG-FET and a QDG-Inverter. These models, built within the architecture of SIMULINK©, are then utilized With the ever-increasing demand for processing power in microelectronic-based devices, the economic impact of the microelectronics industry has blossomed over the past decades. However, fabrication of smaller devices has led to new innovation challenges such as the shrinking of critical dimensions, and the effects of defects and impurities have therein. These considerations, as well as methods and materials being employed to address them, have led to immense costs to both the manufacturer and the consumer. It is for these reasons, an alternative approach to Moore’s law is presented; instead of utilizing techniques to decrease the size of the transistor, quantum dot technology, which allows for the creation of devices with intermediate states, is proposed. The use of quantum dots in the gate and/or channel region of an FET demonstrates more processing power, while inhabiting the same spatial constraints of the chip, rather than physically shrinking the device dimensions. The Quantum Dot Gate (QDG) FET comprises of two or more quantum dot layers in the gate region of a conventional nMOS FET, which allows for the formation of intermediate states. The existence of intermediate states affords the devices the ability to be utilized to create more efficient logic circuits. The first part of this thesis will discuss a physics-based model of both a QDG-FET and a QDG-Inverter. These models, built within the architecture of SIMULINK©, are then utilized