With the advent of globalization and the resulting horizontal integration, present-day electronic component supply chain has become extremely complex and called for immediate solutions to eliminate counterfeit integrated circuits (ICs). Such counterfeit ICs have raised serious concerns regarding the safety and security of military systems, financial infrastructures, transportation, communication, household appliances, and many more applications. Various types of counterfeit ICs - recycled, remarked, overproduced, out-of-spec/defective, cloned, forged documentation, and tampered - have made the supply chain vulnerable to various attacks. However, due to the lack of efficient detection and avoidance techniques, many more instances of counterfeit ICs evade detection than those that are actually detected. Over the past few years, standards and programs have been put in place throughout the supply chain that outline testing, documenting, and reporting procedures for counterfeit IC detection. However, these test methods are mostly designed to detect only recycled and remarked ICs. Moreover, there is little uniformity in the test results among the various entities involved in the test process. Currently, there are no metrics for evaluating counterfeit detection methods. In addition, excessive cost and time to implement these tests make the detection process even challenging. In this research, we have addressed the aforementioned issues by assessing existing test methods with newly developed test metrics, and developing different design-for-anti-counterfeit (DfAC) measures. For the assessment of test methods, we have proposed taxonomies for (i) all different counterfeit IC types currently infiltrating the electronic component supply chain, (ii) defects present in different counterfeit ICs, and (iii) currently available test methods for detecting these ICs. Based on these taxonomies, we have introduced relevant and novel test metrics to evaluate the effectiveness of test methods. We have developed a comprehensive framework (i) for assessing a set of test methods to evaluate their effectiveness based on the newly developed metrics, (ii) selecting a set of test methods to maximize counterfeit defect coverage considering test cost and time budget, and (iii) deciding on the best set of test methods for achieving maximum counterfeit defect coverage (CDC). Due to the sheer number of different component types (digital, analog, and mixed-signal) and sizes (large or small), it becomes extremely difficult to develop a one-size-fits-all DfAC measure to detect and prevent counterfeit ICs. Thus, we have proposed a suite of DfAC measures, which can help us to detect these counterfeit ICs without the need for conventional test methods. First, we propose a group of solutions for combating die and IC recycling (CDIR). These solutions include light-weight, on-chip structures based on ring oscillators (RO-CDIR), and semiconductor fuses (F-CDIR). Each structure meets the unique needs and limitations of different part types and sizes, providing excellent coverage for recycled ICs. Recycled digital ICs can be effectively detected by using RO-CDIR. Any recycled ICs, specifically analog and mixed-signal ICs, can be identified by testing our F-CDIR with very low cost measurement devices, e.g., a multimeter. Second, we have proposed two improved versions of RO-CDIR as it is extremely challenging to detect a recycled IC that has been used for a very short period of time. These versions address the fact that process variations outpace the degradation caused by aging especially in lower technology nodes, making it harder to detect potential recycling by aging degradation. Simulation results demonstrate that these CDIRs can detect ICs used even for a few hours. Finally, we present FORTIS: a comprehensive solution for protecting semiconductor intellectual properties (IPs) and ICs by ensuring forward trust between all entities involved in the system-on-chip (SoC) design and fabrication process. FORTIS is designed to prevent IC overproduction; however, it can be used to prevent other counterfeit types (except recycled ones). FORTIS uses an existing logic encryption technique to obfuscate the netlist of a SoC or a third party IP and allows manufacturing tests before the activation of chips, a feature that is lacking in other competing techniques. In addition, we also propose to attach an IP digest to the IP header to prevent modification of an IP by the SoC designers. We have shown that our approach is resistant to various attacks with the cost of minimal area overhead.
