Low Power CMOS ASICs for Implantable Biosensor Platform and Multi-State SWS-QDC-FET based Memory

Technological advancements in implantable biosensors have led to real-time continuous monitoring of metabolites to achieve proactive health care management. Multianalyte biosensing, as compared to single analyte, can provide a holistic understanding of the body’s metabolism. Complementary metal-oxide-semiconductor (CMOS) electronics for an optical wireless biosensing platform comprise of a sequencer and sensor readout ICs. The objective of the sequencer is to bridge multiple sensors and corresponding readout circuitry into one seamless optical communication path. The first part of the thesis will focus on the development of the sequencer IC realized in 65 nm CMOS technology. We propose a custom CMOS application specific integrated circuit (ASIC) located on the implantable biosensor platform. A pulse modulated LED, located in an external proximity communicator device, optically controls the switching from one sensor electrode to another. The LED signal is received by a photovoltaic (PV) cell located on the ASIC. The ASIC features include: 1) a regulated PV voltage across the biosensing platform, 2) a reference voltage to the potentiostat, 3) multiplexing of the output signals from each sensor read-out circuit and 4) a buffer to drive the output into an LED to transmit information to external proximity communicator. The work focuses on the realization of a sensor readout IC geared to reduce both the size of the implant and its power requirements. The reduced size and power consumption of the chip on the implant system allows this platform to be well suited for miniaturization and minimal invasiveness. Furthermore, this system exhibits improved coupling with photovoltaic power which ensures longer battery life for the external proximity communicator device. The scaling down of MOSFETs played a significant part over the past few decades in achieving higher speed, higher density, and lowering power consumption for integrated chips. As device scaling is reaching its limits, the demand for more information density and higher processing speed provided strong background and motivation towards beyond-binary logic designs i.e., multi-state logic circuits. A spatial wavefunction switched (SWS) Quantum-Dot Channel (QDC) FET has two channels that comprises of four vertically stacked quantum-dots superlattices (QDSLs), providing multiple thresholds within the device, allowing multistate logic and/or storage devices. A two-layer GeOx-cladded Ge QDs or SiOx-cladded Si QDs in an SWS-QDC provides a 4-state/2-bit FET operation. These multistate devices can be implemented for logic computation and storage using static random-access memory (SRAM) and dynamic-random access memory (DRAM). The second part of the thesis presents the design and implementation of peripheral circuits for SWS-QDC based SRAM and DRAM memory cells. The SWS-FET device is modeled by integrating of the Berkeley Short-channel IGFET Model (BSIM4) and the Verilog/Analog Behavioral Model (ABM).