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Description
Field programmable gate arrays (FPGAs) have grown in prominence in recent years
with the advent of large devices containing millions of gates and thousands of DSP
units. To aid in the development of these increasingly complex designs, high-level synthesis
(HLS) tools have been developed and grown in maturity. These tools, in addition
to the previous method of using VHDL designs, have allowed the design of hardware
in a way not previously accessible. Unfortunately, these tools are often optimized for
the speed of producing the designs, not efficiency in the designs. In this dissertation,
we propose the Hardware Optimization Tool for Memory Table and Logic Conversion
(HOTMeTaL), which aims to improve the size and speed of open-source FPGA designs.
After introducing this tool, the output designs of several examples will be given.
Finally, we introduce an FFT based method to solve several types of Toeplitz systems
of equations using fast Fourier transforms (FFTs), along with a possible application and
propose the use of one of the optimized FFTs designs produced by HOTMeTaL.
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