Design and Modeling of Submicron Gallium Arsenide Field-Effect Transistors
Digital Document
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Handle
http://hdl.handle.net/11134/20002:860659601
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Persons |
Persons
Creator (cre): Donkor, Eric
Major Advisor (mja): Jain, Faquir
Associate Advisor (asa): Schultz, Clarence W.
Associate Advisor (asa): Bansal, Rajeev
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Title |
Title
Title
Design and Modeling of Submicron Gallium Arsenide Field-Effect Transistors
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Origin Information
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Parent Item
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Resource Type
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Digital Origin |
Digital Origin
reformatted digital
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Description |
Description
An analytical model is presented to accurately characterize the electrical behavior and to describe in detail, the operation of submicron GaAs FETs. The model expresses device characteristics such as current-voltage characteristics, transconductance, and gate-to-source and gate-to-drain capacitances, in terms of two-dimensional relations. This is made possible through the solution of Poisson's equation for the electrostatic potential in the depletion region of the FET using a perturbation method. This new approach leads to a better agreement between theory and experiment, particularly for scaled down devices, rather than conventional one-dimensional methods. Hot electron transport due to high electric field effects is also included in the method, through a solution in phase space of the momentum-energy balance equations. The description includes both the transient and steady state velocity of the carriers. The transient velocity was calculated for field strength ranging between 1 and 100 kV/cm. The results are contrasted with Monte Carlo Methods. At 100 kV/cm the overshoot velocity was calculated as 9.8 x 107 cm/s and occurred 0.4 picoseconds after turn-on of the field. For submicron FETs, the steady state velocity saturated at 2.38 x 107 cm/s and found to be independent of gate length or active layer thickness. A rapidly convergent sum series expression describes the current-voltage relations. The model accounts for carrier velocity overshoot effects. Numerically computed current-voltage characteristics are compared with experimental results reported in the literature for self-aligned and conventional GaAs FETs with gate length ranging between 0.055 and 0.99p.m. Over 95% agreement was obtained in both the linear and the saturation regions of the current-voltage characteristics. The model for the gate capacitance covers the subthreshold, near threshold and above threshold regimes.
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Genre
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Organizations
Degree granting institution (dgg): University of Connecticut
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Extent
x, 139 leaves, bound : illustrations ; 28 cm
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Rights Statement |
Rights Statement
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Use and Reproduction |
Use and Reproduction
These materials are provided for educational and research purposes only.
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Local Identifier |
Local Identifier
39153020745743
22777706
ASC Thesis 7917
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