Multi-State Memory and Logic Designs Using Multi-Quantum Channel Nano-FETs

In this dissertation, implementation of multi value logic using a novel algebra and Spatial Wavefunction Switched Field Effect Transistor (SWSFET) has been explored. The quantum mechanical simulations, characteristics of the fabricated SWS structures are discussed. The novel device and quaternary algebra has been used to implement multi-value logic. The designs of quaternary SRAM cells, basic logic gates and arithmetic cells are presented. In addition, mixed signal architectures using SWSFET are explored. Simulations for the memory, logic and mixed signal designs are presented. BSIM3 equivalent channel models were used for SWSFET. Cadence Spectre Simulator and Advanced Design Simulator were used as the simulation tools. Quaternary to binary and binary to quaternary conversion circuits are also designed and presented. This helps the quaternary and binary circuits to co-exist on the same die. Multi Valued Logic (MVL) has been in research for many decades. MVL offers benefits and opportunities but it has its own challenges. Quaternary SRAM using SWSFET reduces the number of transistors needed by 75%. Similar savings are shown for implementing quaternary logic when compared to implementation using CMOS based binary logic. In addition, significant reduction in gate delays is achieved by implemented logic using quaternary algebra. Also, logic implementation using quaternary algebra leads to about 50% reduction in interconnect metal density for data signals. This is helpful in reducing the congestion in metal signal routing layers. Metal density, number of metal layers and pressure to use low resistivity materials have added to the die cost over recent years. Implementing MVL in main stream microprocessor needs further research in designs tools. In addition, the fabrication and transistor design need to be optimized to tune MVL based designs.